1. Field
The present disclosure generally relate to a multi-chip modules (MCMs) for semiconductor chips. More specifically, the present disclosure relates to an MCM that includes features that are at least partially sacrificed during assembly of the MCM.
2. Related Art
Three dimensional (3D) chip stacking using through-silicon-vias (TSVs) is an important area of research in developing future high-density, high-performance multi-chip systems. In existing 3D chip stacking TSV techniques, chip-to-wafer and/or chip-to-chip bonding remains a challenging operation because of problems in attaining ultra-high alignment accuracy and high-throughput manufacturing. These difficulties are expected to increase in future multi-chip systems.
For example, in proposed multi-chip systems, die stacking is expected to be implemented in the metal layers below the top metal bond pads, and the target pad size/pitch is expected to decrease from 50-200 μm to 5-10 μm. Furthermore, in order to achieve an all-copper interconnect solution, future multi-chip systems will likely use inter-die stacking between copper nails and copper pads. These techniques are expected to require higher in-plane alignment accuracy, as well as higher co-planarity, than in existing multi-chip systems.
However, existing flip-chip bonders, which can achieve an accuracy of ±1-3 μm, usually have poor manufacturing throughput. Similarly, other alignment techniques that ensure high bonding accuracy are typically not suitable for use in high-volume manufacturing because of the long time needed to bond a single chip. Indeed, low manufacturing throughput often makes bonding one of the most expensive process operations when fabricating TSVs, which, in turn, increases the cost of the resulting multi-chip systems.
Hence, what is needed is a technique for fabricating a multi-chip system without the above-described problems.